A conventional semiconductor memory device typically outputs data at a storage cell position corresponding to an address inputted from a data processing device, such as a memory controller, according to a read command of the data processing device. Furthermore, the conventional semiconductor memory device writes the data inputted from the data processing device at a storage cell position corresponding to the address inputted from the data processing device according to a write command of the data processing device. Conventional semiconductor memory devices are designed to perform write and read operations at high speeds.
In general, semiconductor memory devices are typically evaluated according to the speeds at which they are able to perform the write and read operations. Particularly, the amount of time that the semiconductor memory devices require to process a large amount of data, such as an image, is a very important performance index. In addition, the accuracy with which a system operates stably to transmit the data outputted from the semiconductor memory device, is another important performance index.
A recently developed semiconductor memory device has been designed to input and output 2-bit data between a rising edge and a falling edge of an externally applied system clock CLK, in order to input and output the data at a high speed. Namely, the recently developed semiconductor memory device has been designed to input and output 4-bit data during one period of the system clock CLK. For this, a data clock WCLK having a frequency that is two times higher than that of the system clock is employed in the semiconductor memory device.
In other words, the recently developed semiconductor memory device is able to input and output the 4-bit data during one period of the system clock CLK by using the system clock CLK to receive an address and a command from an external source and by using the data clock WCLK to input and output the data.
FIG. 1 is a diagram illustrating a write operation of a conventional semiconductor memory device.
As shown in FIG. 1, a frequency of a data clock WCLK is two times higher than that of a system clock CLK and the conventional semiconductor memory device receives data DATA corresponding to a write command after synchronizing the data with a rising edge and a falling edge of the data clock WCLK. At this time, the semiconductor memory device is able to accurately receive the data DATA, only when the rising edge and the falling edge of the data clock WCLK exist within a valid window of the data DATA. The valid window is represented by ‘UI’ in the drawing.
Meanwhile, due to the data clock WCLK and a physical delay factor in a data transmitting process, the rising and falling edges of the data clock WCLK may not exist within the valid window of the data DATA and in this case, the semiconductor memory device may receive inaccurate data. Particularly, as the valid window UI of the data becomes smaller and the amount of data increases in a high speed operation system, it becomes increasingly difficult to stably transmit the data.
Recently, conventional semiconductor memory devices have been able to overcome this problem and transmit data at high speeds through data training. The data training includes read training and write training and is a technology that is capable of adjusting a skew between the data and the data clock WCLK by using a predetermined training pattern between a memory controller and the semiconductor memory device in order to stably transmit the data for a read operation and a write operation. A recently suggested semiconductor memory device is designed for high-speed data transmission of more than 4 Gbps and performs the data training to secure reliability of a high-speed operation.